The present invention relates in general to the field of analog-to-digital conversion. More particularly, the present invention relates to a novel analog-to-digital converter circuit for high speed data communication and storage applications.
Flash analog-to-digital converters (ADC""s) are well known in the art. Such devices convert analog signals to corresponding digital signals instantly in parallel, and can be operated at very high speeds, typically up to 500 MHZ. As such, flash A/D converters are especially useful for high-speed data communications and storage applications.
Analog-to-digital conversion in flash devices is made possible by using a voltage divider and a reference voltage at the full-scale of the input range. In a typical flash device, the voltage divider includes 2n resistors in series, where n is the number of bits representing the digital signal and 2n is the analog-to-digital conversion resolution. The digital output of the device corresponding to a given analog input voltage is determined by using a comparator at each of the 2n reference voltages created in the voltage divider. Typically, each comparator is implemented as a complementary metal oxide semiconductor (CMOS) device for added high-speed switching and low power consumption capabilities.
Comparison of the differential inputs and references is typically done using conventional circuits. A first conventional circuit 10, as shown in prior art FIG. 1, employs two CMOS differential pairs, pairs 12 and 16 and 14 and 18, coupled to the positive and negative inputs Vp and Vm of a comparator 20. Note, only one comparator (level) is shown. Such circuits however are usually undesirable for integrated circuit implementation due to their increased area and power dissipation requirements. Also, such circuits are characterized by reduced gain due to lower output impedance, and reduced speed due to larger load capacitance.
A second conventional circuit, as shown in prior art FIG. 2, employs capacitive coupling at the positive and negative inputs Vp and Vm of a voltage comparator 36. Again, only one comparator is shown. Capacitors 32 and 34 are provided at inputs Vp and Vm, respectively, which are used to regulate and limit the differential inputs to Vrefp and Vrefm as determined by capacitance values Cp and Cm. A shortcoming of such a circuit however is that the capacitors 32 and 34 are not easily realizable in combination with the CMOS technologies required for fabricating the amplifier 36. CMOS integrated circuits fabricated with such amplifiers and associated drivers require additional masks and fabrication techniques that add to the cost of the ADC""s.
The aforedescribed limitations and inadequacies of conventional flash analog-to-digital converters (ADC""s) are substantially overcome by the present invention, in which a principal object is to provide a flash analog-to-digital converter (ADC) for comparing a differential input signal with a fully differential reference signal.
Another object of the present invention to provide a fully differential flash ADC that can be easily implemented as a CMOS-based integrated circuit.
Yet another object of the present invention to provide a fully differential flash ADC having a reduced size.
Still another object of the present invention to provide a fully differential flash ADC characterized by low power consumption.
A further object of the present invention to provide a fully differential flash ADC for use in high speed data communication and storage applications.
Accordingly, a fully differential flash ADC is provided for converting an analog differential signal to a corresponding 2n-level (n-bit) digital signal. In accordance with a preferred embodiment of the present invention, the fully differential flash ADC includes 2n voltage comparators each having a first input terminal and a second input terminal for the differential signal, and an output terminal for providing a comparator output signal. A first floating network of 2n resistive elements is provided to which a first analog signal of the differential signal to be converted is applied. The first network includes a plurality of first network nodes coupled to the corresponding comparators via the first input terminals of the voltage comparators. The middle node, or first middle node, is coupled to the first analog signal so as to minimize time constants associated with the first network.
Similarly, a second floating network of 2n resistive elements is provided to which a second analog signal of the differential signal to be converted is applied, the second network having a plurality of second network nodes each coupled to the second input terminal of the corresponding one of the comparators. The middle node of the second network is similarly coupled to the second analog signal for the purpose of minimizing the time constants associated with the second network.
Also, because the ladders are floating, the ladders do not impose any additional drive requirements on the output buffers of the S/H circuit.
Further objects, features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying figures showing illustrative embodiments of the invention.